The present invention is directed to disk memory controller circuits and more particularly, to the topographical layout of disk memory controller circuits which are integrated on semiconductor chips.
A disk memory is a large capacity memory in which digital data is stored on one or more rotating disks. Each disk is usually coated with a ferro-magnetic material. Data is written on the disk by passing a current through a coil in a read/write head positioned adjacent the disk. The current through the coil magnetizes a small area on the disk. The size of the magnetized area generally depends upon the speed of rotation of the disk and the duration of the writing current. To read the data stored on a disk, the coil of the read/write head is used as a sense winding. The movement of a magnetized area under the head induces a voltage in the coil which is sensed by a sense amplifier.
A disk memory controller circuit is provided to control the motion of the head in order to read or write data at a particular location on the disk. In addition, the data to be written on or read from the disk is typically transmitted through the disk controller circuit.
Data to be stored in a disk memory is often stored first in a buffer memory by the central processing unit (CPU) of the computer system. The data is then read from the buffer memory by the disk memory controller circuit and written onto the disk at the disk memory location specified by the CPU. Conversely, in read operations, data read from the disk memory at a location specified by the CPU is transferred by the disk memory controller circuit to the buffer memory.
However, merely designing a circuit to perform these functions is not sufficient to insure that such a circuit will be economical to manufacture as a metal oxide semiconductor (MOS) large scale integrated (LSI) circuit chip. The primary consideration in the economical manufacture of MOS LSI circuits is minimizing the amount of substrate material (such as silicon) required to produce an integrated circuit chip, thus allowing a greater chip yield per substrate wafer.
The surface geometry of the MOS circuitry is formed on a chip and the interconnection pattern of conductors therebetween must be optimized to provide the highest functional component density in order to reduce overall chip area per circuit function. Minimum geometry spacings between metallization lines, diffused regions, and polycrystalline silicon conductors must be maintained, yet the length of such lines and their associated capacitances must be minimized in order to optimize circuit performance as the complex interconnection patterns are implemented. Parasitic electrical effects on the circuitry also must be minimized or compensated for in the chip layout. A very high degree of creativeness is thus required of the chip architect in order to choose a particular layout and interconnection pattern for an LSI circuit from the very large number of possibilities that exist for arranging such a circuit. Frequently, the commercial success of a MOS LSI product may hinge on the ability of a chip architect to achieve an optimum chip topography.
By creatively structuring the topographic layout of the DMC chip, the present invention allows a MOS LSI chip size of 238.2 mils by 245.2 mils, with a processing speed of up to 5 megabits per second, or even more. The preferred embodiment of the present invention is fabricated in N-channel, self-aligned silicon gate MOS technology, and is transistor-transistor logic (TTL) compatible on all inputs and outputs.
It is therefore an object of this invention to provide an optimum chip topography for a MOS LSI disk memory controller circuit.